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Spresense SDK Library v3.3.0-375c679
edid.h
1/****************************************************************************
2 * include/nuttx/video/edid.h
3 * EDID (Extended Display Identification Data) Format
4 *
5 * Copyright (C) 2019 Gregory Nutt. All rights reserved.
6 * Author: Gregory Nutt <gnutt@nuttx.org>
7 *
8 * Reference: Wikipedia (initial version)
9 *
10 * Updated and extended with definitions from FreeBSD which has a compatible
11 * 2-clause BSD license:
12 *
13 * Copyright (c) 2006 Itronix Inc. All rights reserved.
14 * Written by Garrett D'Amore for Itronix Inc.
15 *
16 * Redistribution and use in source and binary forms, with or without
17 * modification, are permitted provided that the following conditions
18 * are met:
19 *
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in
24 * the documentation and/or other materials provided with the
25 * distribution.
26 * 3. Neither the name NuttX nor the names of its contributors may be
27 * used to endorse or promote products derived from this software
28 * without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
33 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
34 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
35 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
36 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
37 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
38 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
40 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
41 * POSSIBILITY OF SUCH DAMAGE.
42 *
43 ****************************************************************************/
44
45#ifndef __INCLUDE_NUTTX_VIDEO_EDID_H
46#define __INCLUDE_NUTTX_VIDEO_EDID_H
47
48/****************************************************************************
49 * Included Files
50 ****************************************************************************/
51
52#include <stdint.h>
53#include <nuttx/video/videomode.h>
54
55/****************************************************************************
56 * Pre-processor Definitions
57 ****************************************************************************/
58
59#define EDID_LENGTH 128
60
61/* EDID data offsets ********************************************************/
62
63/* Bytes 0-7: Header Information */
64
65#define EDID_HEADER_MAGIC_OFFSET 0 /* Fixed header pattern: 00 FF FF FF FF FF FF 00 */
66#define EDID_HEADER_MAGIC_SIZE 8
67
68/* Bytes 8-17: Vendor Information */
69
70#define EDID_VENDOR_MANUFACTURER_OFFSET 8 /* Encoded 3-character manufacture ID */
71#define EDID_VENDOR_MANUFACTURER_SIZE 2 /* 16-bit, big endian value */
72
73#define EDID_VENDOR_PRODUCTCODE_OFFSET 10 /* Product code. 16-bit, little endian value */
74#define EDID_VENDOR_PRODUCTCODE_SIZE 2
75
76#define EDID_VENDOR_SERIALNO_OFFSET 12 /* Serial number: 32-bit, little endian value */
77#define EDID_VENDOR_SERIALNO_SIZE 4
78
79#define EDID_VENDOR_WEEK_OFFSET 16 /* Week of manufacture or model year flag */
80#define EDID_VENDOR_YEAR_OFFSET 17 /* Year of manufacture (minus 1990) */
81
82/* Bytes 18-19: EDID Version */
83
84#define EDID_VERSION_MAJOR_OFFSET 18 /* EDID version, usually 1 (for 1.3) */
85#define EDID_VERSION_MINOR_OFFSET 19 /* EDID revision, usually 3 (for 1.3) */
86
87/* Bytes 20-44: Display Information */
88
89#define EDID_DISPLAY_INPUT_OFFSET 20 /* Video input parameters bitmap */
90#define EDID_DISPLAY_HSIZE_OFFSET 21 /* Horizontal screen size, in centimetres */
91#define EDID_DISPLAY_VSIZE_OFFSET 22 /* Vertical screen size, in centimetres */
92#define EDID_DISPLAY_GAMMA_OFFSET 23 /* Display gamma, factory default */
93#define EDID_DISPLAY_FEATURES_OFFSET 24 /* Support features bitmap */
94
95/* Bytes 25-34: Chromaticity */
96
97#define EDID_CHROMA_RG_LOW_OFFSET 25 /* Red and green least-significant bits (2^9, 2^10) */
98#define EDID_CHROMA_BW_LOW_OFFSET 26 /* Blue and white least-significant 2 bits */
99#define EDID_CHROMA_REDX_OFFSET 27 /* Red x value most significant 8 bits (2^1,...,2^8) */
100#define EDID_CHROMA_REDY_OFFSET 28 /* Red y value most significant 8 bits */
101#define EDID_CHROMA_GREENX_OFFSET 29 /* Green x value most significant 8 bits */
102#define EDID_CHROMA_GREENY_OFFSET 30 /* Green y value most significant 8 bits */
103#define EDID_CHROMA_BLUEX_OFFSET 31 /* Blue x value most significant 8 bits */
104#define EDID_CHROMA_BLUEY_OFFSET 32 /* Blue y value most significant 8 bits */
105#define EDID_CHROMA_WHITEX_OFFSET 33 /* Default white point x value most significant 8 bits */
106#define EDID_CHROMA_WHITEY_OFFSET 34 /* Default white point y value most significant 8 bits */
107
108/* Bytes 35-37: Established timing bitmap */
109
110#define EDID_TIMING_OFFSET_1 35
111#define EDID_TIMING_OFFSET_2 36
112#define EDID_TIMING_OFFSET_3 37
113
114/* Bytes 38-53: Standard Timing Information */
115
116#define EDID_STDTIMING_OFFSET 38 /* Each is size two bytes. */
117#define EDID_STDTIMING_OFFSET_1 38
118#define EDID_STDTIMING_OFFSET_2 40
119#define EDID_STDTIMING_OFFSET_3 42
120#define EDID_STDTIMING_OFFSET_4 44
121#define EDID_STDTIMING_OFFSET_5 45
122#define EDID_STDTIMING_OFFSET_6 48
123#define EDID_STDTIMING_OFFSET_7 50
124#define EDID_STDTIMING_OFFSET_8 52
125
126#define EDID_STDTIMING_NUMBER 8
127#define EDID_STDTIMING_SIZE 2
128
129/* Bytes 54-125: Descriptor Blocks */
130
131#define EDID_DESCRIPTOR_OFFSET 54 /* Each is size 18 bytes */
132#define EDID_DESCRIPTOR_OFFSET_1 54
133#define EDID_DESCRIPTOR_OFFSET_2 72
134#define EDID_DESCRIPTOR_OFFSET_3 90
135#define EDID_DESCRIPTOR_OFFSET_4 108
136
137#define EDID_DESCRIPTOR_NUMBER 4
138#define EDID_DESCRIPTOR_SIZE 18
139
140/* Bits 126-127: Trailer */
141
142#define EDID_TRAILER_NEXTENSIONS_OFFSET 126 /* Number of extensions to follow */
143#define EDID_TRAILER_CHECKSUM_OFFSET 127 /* Checksum. Sum of all 128 bytes should equal 0 */
144
145/* EDID Bitfield Definitions ************************************************/
146
147#define EDID_MAGIC {0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0}
148
149/* Vendor Section: Manufacturer ID */
150
151#define EDID_VENDOR_MANUFACTURER_1(n) ((((n) >> 10) & 0x1f) + '@')
152#define EDID_VENDOR_MANUFACTURER_2(n) ((((n) >> 5) & 0x1f) + '@')
153#define EDID_VENDOR_MANUFACTURER_3(n) ((((n) >> 0) & 0x1f) + '@')
154
155/* Display Section: Display Input */
156
157#define BIT_DEPTH_6 1 /* Values for bit depth */
158#define BIT_DEPTH_8 2
159#define BIT_DEPTH_10 3
160#define BIT_DEPTH_12 4
161#define BIT_DEPTH_14 5
162#define BIT_DEPTH_16 6
163
164#define VIDEO_INTF_HDMIA 1 /* Values for video interface */
165#define VIDEO_INTF_HDMIB 2
166#define VIDEO_INTF_MDDI 4
167#define VIDEO_INTF_DISPLAYPORT 5
168
169#define EDID_DISPLAY_INPUT_DIGITAL (1 << 7) /* Bit 7: Digital input */
170
171 /* For digital input: */
172#define EDID_DISPLAY_INPUT_VIDIF_SHIFT (0) /* Bits 0-3: Video interface */
173#define EDID_DISPLAY_INPUT_VIDIF_MASK (15 << EDID_DISPLAY_INPUT_VIDIF_SHIFT)
174# define EDID_DISPLAY_INPUT_DFP1_COMPAT (1 << EDID_DISPLAY_INPUT_VIDIF_SHIFT)
175#define EDID_DISPLAY_INPUT_BITDEPTH_SHIFT (4) /* Bits 4-6: Bit depth */
176#define EDID_DISPLAY_INPUT_BITDEPTH_MASK (7 << EDID_DISPLAY_INPUT_BITDEPTH_SHIFT)
177
178 /* For analog input: */
179#define EDID_DISPLAY_INPUT_VSERRATED (1 << 0) /* Bit 0: VSync pulse must be serrated
180 * when composite or sync-on-green
181 * is used */
182#define EDID_DISPLAY_INPUT_GREEN (1 << 1) /* Bit 1: Sync on green supported */
183#define EDID_DISPLAY_INPUT_COMPOSITE (1 << 2) /* Bit 2: Composite sync (on HSync)
184 * supported */
185#define EDID_DISPLAY_INPUT_SYNC (1 << 3) /* Bit 3: Separate sync supported */
186#define EDID_DISPLAY_INPUT_BLANK2BLACK (1 << 4) /* Bit 4: Blank to black setup */
187#define EDID_DISPLAY_INPUT_LEVELS_SHIFT (5) /* Bits 5-6: Video white and sync levels,
188 * relative to blank */
189#define EDID_DISPLAY_INPUT_LEVELS_MASK (3 << EDID_DISPLAY_INPUT_LEVELS_SHIFT)
190# define EDID_DISPLAY_INPUT_LEVEL_1 (0 << EDID_DISPLAY_INPUT_LEVELS_SHIFT) /* -0.7, 0.3V */
191# define EDID_DISPLAY_INPUT_LEVEL_2 (1 << EDID_DISPLAY_INPUT_LEVELS_SHIFT) /* -0.714, 0.286V */
192# define EDID_DISPLAY_INPUT_LEVEL_3 (2 << EDID_DISPLAY_INPUT_LEVELS_SHIFT) /* -1.0, 0.4V */
193# define EDID_DISPLAY_INPUT_LEVEL_4 (3 << EDID_DISPLAY_INPUT_LEVELS_SHIFT) /* -0.7, 0.0V */
194
195/* Display Section: Supported Features */
196
197#define ANALOG_DISPLAY_TYPE_MONOCHOME 0 /* Monochrome or Grayscale */
198#define ANALOG_DISPLAY_TYPE_RGB 1 /* RGB color */
199#define ANALOG_DISPLAY_TYPE_NONRGB 2 /* Non-RGB color */
200
201#define DIGITAL_DISPLAY_TYPE_RGB444 0 /* RGB 4:4:4 */
202#define DIGITAL_DISPLAY_TYPE_RGBYCRCB_1 1 /* RGB 4:4:4 + YCrCb 4:4:4 */
203#define DIGITAL_DISPLAY_TYPE_RGBYCRCB_2 2 /* RGB 4:4:4 + YCrCb 4:2:2 */
204#define DIGITAL_DISPLAY_TYPE_RGBYCRCB_3 3 /* RGB 4:4:4 + YCrCb 4:4:4 + YCrCb 4:2:2 */
205
206#define EDID_DISPLAY_FEATURE_CONTINUOUS (1 << 0) /* Bit 0: Continuous timings with GTF
207 * or CVT */
208#define EDID_DISPLAY_FEATURE_MODE (1 << 1) /* Bit 1: Preferred timing mode specified
209 * in descriptor block 1 */
210#define EDID_DISPLAY_FEATURE_STDRGB (1 << 2) /* Bit 2: Standard sRGB colour space */
211#define EDID_DISPLAY_FEATURE_ATYPE_SHIFT (3) /* Bits 3-4: Display type (analog) */
212#define EDID_DISPLAY_FEATURE_ATYPE_MASK (3 << EDID_DISPLAY_FEATURE_ATYPE_SHIFT)
213#define EDID_DISPLAY_FEATURE_DTYPE_SHIFT (3) /* Bits 3-4: Display type (digital) */
214#define EDID_DISPLAY_FEATURE_DTYPE_MASK (3 << EDID_DISPLAY_FEATURE_DTYPE_SHIFT)
215# define EDID_ISPLAY_FEATURES_DTYPE_MONO (0 << EDID_DISPLAY_FEATURE_DTYPE_SHIFT)
216# define EDID_ISPLAY_FEATURES_DTYPE_RGB (1 << EDID_DISPLAY_FEATURE_DTYPE_SHIFT)
217# define EDID_ISPLAY_FEATURES_DTYPE_NON_RGB (2 << EDID_DISPLAY_FEATURE_DTYPE_SHIFT)
218# define EDID_ISPLAY_FEATURES_DTYPE_UNDEFINED (3 << EDID_DISPLAY_FEATURE_DTYPE_SHIFT)
219#define EDID_DISPLAY_FEATURE_DPMSOFF (1 << 5) /* Bit 5: DPMS active-off supported */
220#define EDID_DISPLAY_FEATURE_DPMSSUSP (1 << 6) /* Bit 6: DPMS suspend supported */
221#define EDID_DISPLAY_FEATURE_DPMSSTDBY (1 << 7) /* Bit 7: DPMS standby supported */
222
223/* Chromaticity Section: Red and green least-significant bits */
224
225#define EDID_CHROMA_RG_LOW_GREEN_Y_SHIFT (0) /* Bits 0-1: Green y value least-significant 2 bits */
226#define EDID_CHROMA_RG_LOW_GREEN_Y_MASK (3 << EDID_CHROMA_RG_LOW_GREEN_Y_SHIFT)
227#define EDID_CHROMA_RG_LOW_GREEN_X_SHIFT (2) /* Bits 2-3: Green x value least-significant 2 bits */
228#define EDID_CHROMA_RG_LOW_GREEN_X_MASK (3 << EDID_CHROMA_RG_LOW_GREEN_X_SHIFT)
229#define EDID_CHROMA_RG_LOW_RED_Y_SHIFT (4) /* Bits 4-5: Red y value least-significant 2 bits */
230#define EDID_CHROMA_RG_LOW_RED_Y_MASK (3 << EDID_CHROMA_RG_LOW_RED_Y_SHIFT)
231#define EDID_CHROMA_RG_LOW_RED_X_SHIFT (6) /* Bits 6-7: Red x value least-significant 2 bits */
232#define EDID_CHROMA_RG_LOW_RED_X_MASK (3 << EDID_CHROMA_RG_LOW_RED_X_SHIFT)
233
234#define EDID_CHROMA_BW_LOW_WHITE_Y_SHIFT (0) /* Bits 0-1: White y value least-significant 2 bits */
235#define EDID_CHROMA_BW_LOW_WHITE_Y_MASK (3 << EDID_CHROMA_BW_LOW_WHITE_Y_SHIFT)
236#define EDID_CHROMA_BW_LOW_WHITE_X_SHIFT (2) /* Bits 2-3: White x value least-significant 2 bits */
237#define EDID_CHROMA_BW_LOW_WHITE_X_MASK (3 << EDID_CHROMA_BW_LOW_WHITE_X_SHIFT)
238#define EDID_CHROMA_BW_LOW_BLUE_Y_SHIFT (4) /* Bits 4-5: Blue y value least-significant 2 bits */
239#define EDID_CHROMA_BW_LOW_BLUE_Y_MASK (3 << EDID_CHROMA_BW_LOW_BLUE_Y_SHIFT)
240#define EDID_CHROMA_BW_LOW_BLUE_X_SHIFT (6) /* Bits 6-7: Blue x value least-significant 2 bits */
241#define EDID_CHROMA_BW_LOW_BLUE_X_MASK (3 << EDID_CHROMA_RG_LOW_RED_X_SHIFT)
242
243#define _CHLO(b,s) (((b) >> (s)) & 0x3)
244#define _CHHI(b) ((b) << 2)
245#define _CHHILO(p,l,s,h) (_CHLO((p)[l], s) | _CHHI((p)[h]))
246#define _CHROMA(p,l,s,h) ((_CHHILO(p,l,s,h) * 1000) / 1024)
247
248#define EDID_CHROMA_RED_X(p) \
249 (_CHROMA(p, EDID_CHROMA_RG_LOW_OFFSET, EDID_CHROMA_RG_LOW_RED_X_SHIFT, \
250 EDID_CHROMA_REDX_OFFSET))
251#define EDID_CHROMA_RED_Y(p) \
252 (_CHROMA(p, EDID_CHROMA_RG_LOW_OFFSET, EDID_CHROMA_RG_LOW_RED_Y_SHIFT, \
253 EDID_CHROMA_REDY_OFFSET))
254#define EDID_CHROMA_GREEN_X(p) \
255 (_CHROMA(p, EDID_CHROMA_RG_LOW_OFFSET, EDID_CHROMA_RG_LOW_GREEN_X_SHIFT, \
256 EDID_CHROMA_GREENX_OFFSET))
257#define EDID_CHROMA_GREEN_Y(p) \
258 (_CHROMA(p, EDID_CHROMA_RG_LOW_OFFSET, EDID_CHROMA_RG_LOW_GREEN_Y_SHIFT, \
259 EDID_CHROMA_GREENY_OFFSET))
260#define EDID_CHROMA_BLUE_X(p) \
261 (_CHROMA(p, EDID_CHROMA_BW_LOW_OFFSET, EDID_CHROMA_BW_LOW_BLUE_X_SHIFT, \
262 EDID_CHROMA_BLUEX_OFFSET))
263#define EDID_CHROMA_BLUE_Y(p) \
264 (_CHROMA(p, EDID_CHROMA_BW_LOW_OFFSET, EDID_CHROMA_BW_LOW_BLUE_Y_SHIFT, \
265 EDID_CHROMA_BLUEY_OFFSET))
266#define EDID_CHROMA_WHITE_X(p) \
267 (_CHROMA(p, EDID_CHROMA_BW_LOW_OFFSET, EDID_CHROMA_BW_LOW_WHITE_X_SHIFT, \
268 EDID_CHROMA_WHITEX_OFFSET))
269#define EDID_CHROMA_WHITE_Y(p) \
270 (_CHROMA(p, EDID_CHROMA_BW_LOW_OFFSET, EDID_CHROMA_BW_LOW_WHITE_Y_SHIFT, \
271 EDID_CHROMA_WHITEY_OFFSET))
272
273/* Bytes 35-37: Established timing bitmap */
274
275#define EDID_TIMING_1_800x600_60Hz (1 << 0)
276#define EDID_TIMING_1_800x600_56Hz (1 << 1)
277#define EDID_TIMING_1_640x600_75Hz (1 << 2)
278#define EDID_TIMING_1_640x480_72Hz (1 << 3)
279#define EDID_TIMING_1_640x480_67Hz (1 << 4)
280#define EDID_TIMING_1_640x480_60Hz (1 << 5)
281#define EDID_TIMING_1_720x400_88Hz (1 << 6)
282#define EDID_TIMING_1_720x400_70Hz (1 << 7)
283
284#define EDID_TIMING_2_1280x1024_75Hz (1 << 0)
285#define EDID_TIMING_2_1024x768_75Hz (1 << 1)
286#define EDID_TIMING_2_1024x768_70Hz (1 << 2)
287#define EDID_TIMING_2_1024x768_60Hz (1 << 3)
288#define EDID_TIMING_2_1024x768_87Hz (1 << 4)
289#define EDID_TIMING_2_832x624_75Hz (1 << 5)
290#define EDID_TIMING_2_800x600_75Hz (1 << 6)
291#define EDID_TIMING_2_800x600_72Hz (1 << 7)
292
293#define EDID_TIMING_3_VENDOR_SHIFT (0) /* Bits 0-6: Manufacturer-specific display modes */
294#define EDID_TIMING_3_VENDOR_MASK (0x7f << EDID_TIMING_3_VENDOR_SHIFT)
295#define EDID_TIMING_3_1152x870_75Hz (1 << 7)
296
297/* Standard Timing Information */
298
299#define ASPECT_RATIO_16_10 0 /* Aspect ratio: 16:10 */
300#define ASPECT_RATIO_4_3 1 /* Aspect ratio: 4:3 */
301#define ASPECT_RATIO_5_4 2 /* Aspect ratio: 5:4 */
302#define ASPECT_RATIO_16_9 3 /* Aspect ratio: 16:9 */
303
304#define EDID_STDTIMING_XRES_OFFSET (0) /* Byte 0: X resolution, divided by 8, less 31 */
305# define EDID_STDTIMING_ASPECT_SHIFT (6) /* Bits 6-7: Image aspect ratio */
306# define EDID_STDTIMING_ASPECT_MASK (3 << EDID_STDTIMING_ASPECT_SHIFT)
307# define EDID_STDTIMING_ASPECT_16_10 (ASPECT_RATIO_16_10 << EDID_STDTIMING_ASPECT_SHIFT)
308# define EDID_STDTIMING_ASPECT_4_3 (ASPECT_RATIO_4_3 << EDID_STDTIMING_ASPECT_SHIFT)
309# define EDID_STDTIMING_ASPECT_5_4 (ASPECT_RATIO_5_4 << EDID_STDTIMING_ASPECT_SHIFT)
310# define EDID_STDTIMING_ASPECT_16_9 (ASPECT_RATIO_16_9 << EDID_STDTIMING_ASPECT_SHIFT)
311# define EDID_STDTIMING_VFREQ_SHIFT (0) /* Bits 0-5: Vertical frequency, less 60 */
312# define EDID_STDTIMING_VFREQ_MASK (0x3f << EDID_STDTIMING_VFREQ_SHIFT)
313
314#define EDID_STDTIMING_INFO_OFFSET (1) /* Byte 1: Image Aspect Ratio / Vertical Frequency */
315
316/* Display Descriptor: EDID Detailed Timing Descriptor */
317
318#define EDID_STEROMODE_FIELDSEQ_RIGHT 1 /* Field sequential, sync=1 during right (bit0=0) */
319#define EDID_STEROMODE_FIELDSEQ_LEFT 2 /* Field sequential, sync=1 during left (bit0=0) */
320#define EDID_STEROMODE_4WAY_INTERLEAVED 3 /* 4-way interleaved stereo (bit0=0) */
321
322#define EDID_STEROMODE_RIGHT 1 /* Right image on even lines (bit0=1) */
323#define EDID_STEROMODE_LEFT 2 /* Left image on even lines (bit0=1) */
324#define EDID_STEROMODE_SIDEBYSIDE 3 /* Side-by-side (bit0=1) */
325
326#define EDID_DESC_PIXCLOCK_OFFSET 0 /* Bytes 0-1: Pixel clock in 10 kHz units */
327#define EDID_DESC_HPIXELS_LSBITS_OFFSET 2 /* Byte 2: Horizontal active pixels 8 LS bits */
328#define EDID_DESC_HBLANK_LSBITS_OFFSET 3 /* Byte 3: Horizontal blanking pixels 8 LS bits */
329#define EDID_DESC_HMSBITS_OFFSET 4 /* Byte 4: Horizontal MS bits */
330# define EDID_DESC_HBLANK_MSBITS_SHIFT (0) /* Bits 0-3: Horizontal blanking pixels 4 MS bits */
331# define EDID_DESC_HBLANK_MSBITS_MASK (15 << EDID_DESC_HBLANK_MSBITS_SHIFT)
332# define EDID_DESC_HPIXELS_MSBITS_SHIFT (4) /* Bits 4-7: Horizontal active pixels 4 MS bits */
333# define EDID_DESC_HPIXELS_MSBITS_MASK (15 << EDID_DESC_HPIXELS_MSBITS_SHIFT)
334#define EDID_DESC_VLINES_LSBITS_OFFSET 5 /* Byte 5: Vertical active lines 8 LS bits */
335#define EDID_DESC_VBLANK_LSBITS_OFFSET 6 /* Byte 6: Vertical blanking lines 8 LS bits */
336#define EDID_DESC_VMSBITS_OFFSET 7 /* Byte 7: Vertical MS bits */
337# define EDID_DESC_VBLANK_MSBITS_SHIFT (0) /* Bits 0-3: Vertical blanking lines 4 MS bits */
338# define EDID_DESC_VBLANK_MSBITS_MASK (15 << EDID_DESC_VBLANK_MSBITS_SHIFT)
339# define EDID_DESC_VLINES_MSBITS_SHIFT (4) /* Bits 4-7: Vertical active lines 4 MS bits */
340# define EDID_DESC_VLINES_MSBITS_MASK (15 << EDID_DESC_VLINES_MSBITS_SHIFT)
341#define EDID_DESC_HPORCH_LSBITS_OFFSET 8 /* Byte 8: Horizontal front porch pixels 8 LS bits */
342#define EDID_DESC_HPW_LSBITS_OFFSET 9 /* Byte 9: Horizontal sync pulse width pixels 8 LS bits */
343#define EDID_DESC_VPORCH_LSBITS_OFFSET 10 /* Byte 10: Vertical front porch and pulsewidth LS bits */
344# define EDID_DESC_VPW_LSBITS_SHIFT (0) /* Bits 0-3: Vertical sync pulsewidth 4 LS bits */
345# define EDID_DESC_VPW_LSBITS_MASK (15 << EDID_DESC_VPW_LSBITS_SHIFT)
346# define EDID_DESC_VPORCH_LSBITS_SHIFT (4) /* Bits 4-7: Vertical front portch 4 LS bits */
347# define EDID_DESC_VPORCH_LSBITS_MASK (15 << EDID_DESC_VPORCH_LSBITS_SHIFT)
348#define EDID_DESC_PORCH_MSBITS_OFFSET 11 /* Byte 11: Vertical MS bits */
349# define EDID_DESC_VPW_MSBITS_SHIFT (0) /* Bits 0-1: Vertical sync pulsewidth lines 2 MS bits */
350# define EDID_DESC_VPW_MSBITS_MASK (3 << EDID_DESC_VPW_MSBITS_SHIFT)
351# define EDID_DESC_VPORCH_MSBITS_SHIFT (2) /* Bits 2-3: Vertical front porch lines 2 MS bits */
352# define EDID_DESC_VPORCH_MSBITS_MASK (3 << EDID_DESC_VPORCH_MSBITS_SHIFT)
353# define EDID_DESC_HPW_MSBITS_SHIFT (4) /* Bits 4-5: Horizontal sync pulsewidth pixels 2 MS bits */
354# define EDID_DESC_HPW_MSBITS_MASK (3 << EDID_DESC_HPW_MSBITS_SHIFT)
355# define EDID_DESC_HPORCH_MSBITS_SHIFT (6) /* Bits 6-7: Horizontal front porch pixels 2 MS bits */
356# define EDID_DESC_HPORCH_MSBITS_MASK (3 << EDID_DESC_HPORCH_MSBITS_SHIFT)
357#define EDID_DESC_HSIZE_LSBITS_OFFSET 12 /* Byte 12: Horizontal image size, mm, 8 LS bits */
358#define EDID_DESC_VSIZE_LSBITS_OFFSET 13 /* Byte 13: Vertical image size, mm, 8 LS bits */
359#define EDID_DESC_SIZE_MSBITS_OFFSET 14 /* Byte 14: Image size MS bits */
360# define EDID_DESC_VSIZE_MSBITS_SHIFT (0) /* Bits 0-3: Vertical image size, mm, 4 MS bits */
361# define EDID_DESC_VSIZE_MSBITS_MASK (15 << EDID_DESC_VSIZE_MSBITS_SHIFT)
362# define EDID_DESC_HSIZE_MSBITS_SHIFT (4) /* Bits 4-7: Horizontal image size, mm, 4 MS bits */
363# define EDID_DESC_HSIZE_MSBITS_MASK (15 << EDID_DESC_HSIZE_MSBITS_SHIFT)
364#define EDID_DESC_HBORDER_OFFSET 15 /* Byte 15: Horizontal border pixels (one side) */
365#define EDID_DESC_VBORDER_OFFSET 16 /* Byte 16: Vertical border lines (one side) */
366#define EDID_DESC_FEATURES_OFFSET 17 /* Byte 17: Features bitmap */
367 /* If bits 5-6=00: */
368# define EDID_DESC_STEREO_INTERLEAVE (1 << 0) /* Bit 0: 2-way line-interleaved or side-by-side
369 * interleaved stereo */
370 /* If bits 3-4=0x: */
371# define EDID_DESC_ANALOG_SYNCALL (1 << 1) /* Bit 1: Sync on all 3 RGB lines (else green only) */
372# define EDID_DESC_ANALOG_VSERRATION (1 << 2) /* Bit 2: VSync serration */
373# define EDID_DESC_ANALOG_SYNCTYPE (1 << 3) /* Bit 3: 0=Analog composite; 1=Bipolar analog composite */
374 /* If bits 3-4=10: */
375# define EDID DESC_DIGITAL_VPOLARITY (1 << 2) /* Bit 2: Vertical sync polarity (0=negative, 1=positive) */
376 /* If bits 3-4=11: */
377# define EDID_DESC_DIGITAL_HPOLARITY (1 << 1) /* Bit 1: Horizontal Sync polarity (0=negative, 1=positive) */
378# define EDID_DESC_DIGITAL_VSERRATION (1 << 2) /* Bit 2: VSync serration */
379# define EDID_DESC_DIGITAL_SYNCTYPE (1 << 3) /* Bit 3: 0=Digital composite; 1=Digital separate sync */
380# define EDID_DESC_DIGITAL_SYNC (1 << 4) /* Bit 4: Digital sync */
381# define EDID_DESC_STEREO_SHIFT (5) /* Bits 5-6: Stero mode */
382# define EDID_DESC_STEREO_MASK (3 << EDID_DESC_STEREO_SHIFT)
383# define EDID_DESC_INTERLACED (1 << 7) /* Bit 7: Interlaced */
384
385/* Descriptor helpers */
386
387#define _VACT_LO(p) ((p)[EDID_DESC_VLINES_LSBITS_OFFSET])
388#define _VBLK_LO(p) ((p)[EDID_DESC_VBLANK_LSBITS_OFFSET])
389#define _VACT_HI(p) (((p)[EDID_DESC_VMSBITS_OFFSET] & EDID_DESC_VLINES_MSBITS_MASK) << 4)
390#define _VBLK_HI(p) (((p)[EDID_DESC_VMSBITS_OFFSET] & EDID_DESC_VBLANK_MSBITS_MASK) << 8)
391#define EDID_DESC_VACTIVE(p) (_VACT_LO(p) | _VACT_HI(p))
392#define EDID_DESC_VBLANK(p) (_VBLK_LO(p) | _VBLK_HI(p))
393
394#define _HACT_LO(p) ((p)[EDID_DESC_HPIXELS_LSBITS_OFFSET])
395#define _HBLK_LO(p) ((p)[EDID_DESC_HBLANK_LSBITS_OFFSET])
396#define _HACT_HI(p) (((p)[EDID_DESC_HMSBITS_OFFSET] & EDID_DESC_HPIXELS_MSBITS_SHIFT) << 4)
397#define _HBLK_HI(p) (((p)[EDID_DESC_HMSBITS_OFFSET] & EDID_DESC_HBLANK_MSBITS_SHIFT) << 8)
398#define EDID_DESC_HACTIVE(p) (_HACT_LO(p) | _HACT_HI(p))
399#define EDID_DESC_HBLANK(p) (_HBLK_LO(p) | _HBLK_HI(p))
400
401#define _HOFF_LO(p) ((p)[EDID_DESC_HPORCH_LSBITS_OFFSET])
402#define _HWID_LO(p) ((p)[EDID_DESC_HPW_LSBITS_OFFSET])
403#define _VOFF_LO(p) ((p)[EDID_DESC_VPORCH_LSBITS_OFFSET] >> EDID_DESC_VPORCH_LSBITS_SHIFT)
404#define _VWID_LO(p) ((p)[EDID_DESC_VPORCH_LSBITS_OFFSET] & EDID_DESC_VPW_LSBITS_MASK)
405#define _HOFF_HI(p) (((p)[EDID_DESC_PORCH_MSBITS_OFFSET] & EDID_DESC_HPORCH_MSBITS_MASK) << 2)
406#define _HWID_HI(p) (((p)[EDID_DESC_PORCH_MSBITS_OFFSET] & EDID_DESC_HPW_MSBITS_MASK) << 4)
407#define _VOFF_HI(p) (((p)[EDID_DESC_PORCH_MSBITS_OFFSET] & EDID_DESC_VPORCH_MSBITS_MASK) << 2)
408#define _VWID_HI(p) (((p)[EDID_DESC_PORCH_MSBITS_OFFSET] & EDID_DESC_VPW_MSBITS_MASK) << 4)
409#define EDID_DESC_HSYNC_OFFSET(p) (_HOFF_LO(p) | _HOFF_HI(p))
410#define EDID_DESC_HSYNC_WIDTH(p) (_HWID_LO(p) | _HWID_HI(p))
411#define EDID_DESC_VSYNC_OFFSET(p) (_VOFF_LO(p) | _VOFF_HI(p))
412#define EDID_DESC_VSYNC_WIDTH(p) (_VWID_LO(p) | _VWID_HI(p))
413
414#define _HSZ_LO(p) ((p)[EDID_DESC_HSIZE_LSBITS_OFFSET])
415#define _VSZ_LO(p) ((p)[EDID_DESC_VSIZE_LSBITS_OFFSET])
416#define _HSZ_HI(p) (((p)[EDID_DESC_SIZE_MSBITS_OFFSET] & EDID_DESC_HSIZE_MSBITS_MASK) << 4)
417#define _VSZ_HI(p) (((p)[EDID_DESC_SIZE_MSBITS_OFFSET] & EDID_DESC_VSIZE_MSBITS_MASK) << 8)
418#define EDID_DESC_HSIZE(p) (_HSZ_LO(p) | _HSZ_HI(p))
419#define EDID_DESC_VSIZE(p) (_VSZ_LO(p) | _VSZ_HI(p))
420
421/* Display Descriptor: EDID Other Monitor Descriptors */
422
423#define EDID_DESC_ZERO_1 0 /* Bytes 0-1: Zero=not a detailed timing descriptor */
424#define EDID_DESC_ZERO_2 2 /* Byte 2: Zero */
425#define EDID_DESC_DESCTYPE 3 /* Byte 3: Descriptor type */
426#define EDID_DESC_ZERO_3 4 /* Byte 4: Zero */
427#define EDID_DESC_INFO 5 /* Bytes 5-17: Determined by descriptor type */
428
429/* 0x00-0x0f: Manufacturer reserved descriptors */
430
431#define EDID_DESCTYPE_DUMMY 0x10 /* Dummy identifier */
432#define EDID_DESCTYPE_STDTIMING 0xf7 /* Additional standard timing 3 */
433#define EDID_DESCTYPE_CVT 0xf8 /* CVT 3-Byte Timing Codes */
434#define EDID_DESCTYPE_DCM 0xf9 /* Display Color Management (DCM) */
435#define EDID_DESCTYPE_STDTIMING_ID 0xfa /* Additional standard timing identifiers */
436#define EDID_DESCTYPE_WHITEPOINT 0xfb /* Additional white point data */
437#define EDID_DESCTYPE_NAME 0xfc /* Display name (ASCII text) */
438#define EDID_DESCTYPE_LIMITS 0xfd /* Display range limits */
439#define EDID_DESCTYPE_TEXT 0xfe /* Unspecified text (ASCII text) */
440#define EDID_DESCTYPE_SERIALNO 0xff /* Display serial number (ASCII text) */
441
442/* Used for descriptors 0xff, 0xfe, and 0xfc */
443
444#define EDID_DESC_ASCII_DATA_OFFSET 5
445#define EDID_DESC_ASCII_DATA_LEN 13
446
447#define EDID_DESC_RANGE_MIN_VFREQ(p) ((p)[5]) /* Hz */
448#define EDID_DESC_RANGE_MAX_VFREQ(p) ((p)[6]) /* Hz */
449#define EDID_DESC_RANGE_MIN_HFREQ(p) ((p)[7]) /* kHz */
450#define EDID_DESC_RANGE_MAX_HFREQ(p) ((p)[8]) /* kHz */
451#define EDID_DESC_RANGE_MAX_CLOCK(p) (((p)[9]) * 10) /* MHz */
452#define EDID_DESC_RANGE_HAVE_GTF2(p) (((p)[10]) == 0x02)
453#define EDID_DESC_RANGE_GTF2_HFREQ(p) (((p)[12]) * 2)
454#define EDID_DESC_RANGE_GTF2_C(p) (((p)[13]) / 2)
455#define EDID_DESC_RANGE_GTF2_M(p) ((p)[14] + ((p)[15] << 8))
456#define EDID_DESC_RANGE_GTF2_K(p) ((p)[16])
457#define EDID_DESC_RANGE_GTF2_J(p) ((p)[17] / 2)
458
459#define EDID_DESC_COLOR_WHITEX(p)
460#define EDID_DESC_COLOR_WHITE_INDEX_1(p) ((p)[5])
461#define EDID_DESC_COLOR_WHITEX_1(p) _CHROMA(p, 6, 2, 7)
462#define EDID_DESC_COLOR_WHITEY_1(p) _CHROMA(p, 6, 0, 8)
463#define EDID_DESC_COLOR_GAMMA_1(p) _GAMMA(p[9])
464#define EDID_DESC_COLOR_WHITE_INDEX_2(p) ((p)[10])
465#define EDID_DESC_COLOR_WHITEX_2(p) _CHROMA(p, 11, 2, 12)
466#define EDID_DESC_COLOR_WHITEY_2(p) _CHROMA(p, 11, 0, 13)
467#define EDID_DESC_COLOR_GAMMA_2(p) _GAMMA(p[14])
468
469#define EDID_DESC_STD_TIMING_START_OFFSET 5
470#define EDID_DESC_STD_TIMING_COUNT_OFFSET 6
471
472/* Extended EDID data offsets ***********************************************/
473
474/* To be provided */
475
476/* EDID Extensions assigned by VESA (First byte of the Extended EDID block) */
477
478#define EDID_EXT_TIMING 0x00 /* Timing Extension */
479#define EDID_EXT_CEA 0x02 /* Additional Timing Data Block (CEA EDID Timing Extension) */
480#define EDID_EXT_VTBEXT 0x10 /* Video Timing Block Extension (VTB-EXT) */
481#define EDID_EXT_V2p0 0x20 /* EDID 2.0 Extension */
482#define EDID_EXT_DIEXT 0x40 /* Display Information Extension (DI-EXT) */
483#define EDID_EXT_LSEXT 0x50 /* Localized String Extension (LS-EXT) */
484#define EDID_EXT_MIEXT 0x60 /* Microdisplay Interface Extension (MI-EXT) */
485#define EDID_EXT_DIDEXIT 0x70 /* Display ID Extension */
486#define EDID_EXT_DTCDB_1 0xa7 /* Display Transfer Characteristics Data Block (DTCDB) */
487#define EDID_EXT_DTCDB_2 0xaf /* Display Transfer Characteristics Data Block (DTCDB) */
488#define EDID_EXT_DTCDB_3 0xbf /* Display Transfer Characteristics Data Block (DTCDB) */
489#define EDID_EXT_BLOCKMAP 0xf0 /* Block Map */
490#define EDID_EXT_DDDB 0xff /* Display Device Data Block (DDDB) */
491#define EDID_EXT_VENDOR 0xff /* Extension defined by monitor manufacturer.
492 * According to LS-EXT, actual contents varies
493 * from manufacturer. However, the value is
494 * later used by DDDB. */
495
496/****************************************************************************
497 * Pre-processor Definitions
498 ****************************************************************************/
499
500/* These structures is a user-friendly digest of the EDID data. */
501
502struct edid_chroma_s
503{
504 uint16_t ec_redx;
505 uint16_t ec_redy;
506 uint16_t ec_greenx;
507 uint16_t ec_greeny;
508 uint16_t ec_bluex;
509 uint16_t ec_bluey;
510 uint16_t ec_whitex;
511 uint16_t ec_whitey;
512};
513
514struct edid_range_s
515{
516 uint16_t er_min_vfreq; /* Hz */
517 uint16_t er_max_vfreq; /* Hz */
518 uint16_t er_min_hfreq; /* kHz */
519 uint16_t er_max_hfreq; /* kHz */
520 uint16_t er_max_clock; /* MHz */
521 uint16_t er_gtf2_hfreq;
522
523 bool er_have_gtf2;
524 uint16_t er_gtf2_c;
525 uint16_t er_gtf2_m;
526 uint16_t er_gtf2_k;
527 uint16_t er_gtf2_j;
528};
529
530struct edid_info_s
531{
532 uint8_t edid_manufacturer[4];
533 uint8_t edid_version;
534 uint8_t edid_revision;
535 uint8_t edid_video_input;
536 uint8_t edid_max_hsize; /* in cm */
537 uint8_t edid_max_vsize; /* in cm */
538 uint8_t edid_gamma;
539 uint8_t edid_features;
540 uint8_t edid_ext_block_count;
541 uint16_t edid_product;
542 uint32_t edid_serial;
543 uint16_t edid_year;
544 uint8_t edid_week;
545 bool edid_have_range;
546
547 struct edid_range_s edid_range;
548 struct edid_chroma_s edid_chroma;
549
550 /* Parsed modes */
551
552 FAR struct videomode_s *edid_preferred_mode;
553 int edid_nmodes;
554 struct videomode_s edid_modes[64];
555};
556
557/****************************************************************************
558 * Public Function Prototypes
559 ****************************************************************************/
560
561/****************************************************************************
562 * Name: edid_parse
563 *
564 * Description:
565 * Given a block of raw EDID data, parse the data and convert it to the
566 * 'digested' form of struct edid_info_s.
567 *
568 * Input Parameters:
569 * data - A reference to the raw EDID data
570 * edid - The location to return the digested EDID data.
571 *
572 * Returned Value:
573 * Zero (OK) is returned on success; otherwise a negated errno value is
574 * returned to indicate the nature of the failure.
575 *
576 ****************************************************************************/
577
578int edid_parse(FAR const uint8_t *data, FAR struct edid_info_s *edid);
579
580/****************************************************************************
581 * Name: edid_dump
582 *
583 * Description:
584 * Dump the full content of the EDID
585 *
586 * Input Parameters:
587 * edid - The edid to be dumped
588 *
589 * Returned Value:
590 * None
591 *
592 ****************************************************************************/
593
594void edid_dump(FAR const struct edid_info_s *edid);
595
596#endif /* __INCLUDE_NUTTX_VIDEO_EDID_H */
edid_chroma_s
Definition: edid.h:493
edid_info_s
Definition: edid.h:521
edid_range_s
Definition: edid.h:505
videomode_s
Definition: videomode.h:84